`include "common_def.v"
`define WAIT_ADDR 1'b0
`define WAIT_DATA 1'b1
module MODULE_IFU(
	input 								clk_i,
	input									rst_i,
	output								if_end_o,
	input									if_start_i,
	//connected to REGS
	input		[`WIDTH-1:0] 	pc_i,	
	//connect to IDU 
	output 	[31:0]				inst_to_IDU_o,
	//connect to LSU
	output 	[`WIDTH-1:0]	pc_o,
	output								addr_valid_o,	
	input		[31:0]				inst_i,
	input									inst_valid_i
);
wire [31:0] inst1;
Reg #(32,0) inst_r (clk_i,rst_i,inst_i[31:0],inst1[31:0],inst_valid_i);
assign inst_to_IDU_o = inst_valid_i ? inst_i[31:0]:inst1[31:0];
assign if_end_o = inst_valid_i;
assign pc_o[`WIDTH-1:0] = pc_i[`WIDTH-1:0];

wire if_start_r;
Reg #(1,0) if_start_reg(clk_i,rst_i,if_end_o? 1'b0:if_start_i,if_start_r,if_start_i|if_end_o);
assign addr_valid_o = (if_start_i | if_start_r) &(~if_end_o);
endmodule
